phase-locked loop detector

英 [feɪz lɒkt luːp dɪˈtektə(r)]

美 [feɪz lɑːkt luːp dɪˈtektər]

网络锁相环路检波器

An adaptive Phase-Locked Loop ( PLL) with a fast settling time and its key blocks including Phase-Frequency Detector ( PFD) and charge pump are then proposed and analyzed.
提出并分析了一种自适应的具有快速建立时间的锁相环结构及其关键模块（鉴相鉴频器和电荷泵）。
A digital phase-locked loop ( DPLL) based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range, low jitter, and fast acquisition.
提出了一种数字锁相环（DPLL），它的相频检测器采用全新的设计方法和自校准技术，具有工作频率范围宽，抖动低，快速锁定的优点。
This paper discusses an all digital phase-locked loop with a zero-crossing detector and a loop filter.
本文讨论的全数字锁相环包括过零检测器和环路滤波器。
The Performance of a Digital Phase-Locked Loop with a Zero-Crossing Detector
使用过零检测器的数字锁相环的性能
This system was based on the existing phase-locked loop technology. The Gaussian window function algorithm was introduced in the architecture. It can improve the accuracy of the phase detector and the phase of the clock signal.
在该锁相环构架中，引入了高斯窗函数算法，使得数字部分的鉴相精度提高，时钟信号的相位更加准确。